Graphics memories which include a plurality of random access memory (RAM) integrated circuits, typically arrange the data transfer in terms of a horizontally contiguous line segment. For instance, if the graphics memory includes 64 RAM's having a single data bit, the single data bits are serialized to form a single 64 pixel, horizontal line on the display device screen. The 64 pixels comprise a word, and the screen bit map is then represented by a sufficient number of words extending horizontally to complete the horizontal line at as many lines arranged vertically to fill the entire screen for the desired resolution. Obviously, for horizontal scanning display devices, such as the conventional NTSC Monitor, the horizontally contiguous arrangement of the RAM data signals provides rapid signal transfer. However, access to the graphics memory in any other geometric relationship, such as a vertical or diagonal line, or a two-dimensional area, requires more complex and time consuming graphics memory access arrangements. For instance, a vertical line would require 64 separate memory word transfer to access the 64 vertical pixels, by contrast with the single memory access necessary to provide the horizontal 64 pixel segment.
An alternate arrangement of the data from the individual RAM integrated circuits is suggested by Sproull, wherein the 64 elements are arranged in a two-dimensional 8.times.8 pixel portion of the graphics memory bit map. While some timing economies are achieved when the desired 8.times.8 area coincides with the boundary of the 8.times.8 portion, the access to data in arbitrarily aligned 8.times.8 portions require at least two row address strobe (RAS) cycles to access the patch, and additional time lost in subsequent data manipulation. More significantly, the organization of memory access to provide the 8.times.8 pixel access does not facilitate memory access in line mode, thereby requiring multiple access cycles and the addition of a separate line mode buffer for time access.